High-performance avionics and defense applications (including radar) are sensitive to the power constraints of most airborne systems. With limited power, establishing the optimal balance between processing performance and power consumption is critical for every embedded system. These systems have the longest product life cycles in the industry, often measured in decades rather than years, so reliability and longevity are also key factors in selecting an embedded system.

Applications such as electronic warfare, signals intelligence, military, surveillance and weather radar, military aircraft and general aviation control systems all require high-throughput, high-speed data acquisition and processing. Before distributing data to end users in real time, these systems need to be able to extract huge amounts of data from the signal, applying powerful signal processing algorithms on the raw data to improve accuracy and precision.

TI's 66AK2L06 system-on-chip (SoC) enables designers of radar applications to improve performance in terms of system cost, size, weight and power (SWaP) on top of current solutions. The integration of the JESD204B interface with the 66AK2L06 SoC not only reduces the complexity of system design, but also reduces the space requirements for radar applications.

The SoC's integration of a programmable digital front end (DFE) allows for adaptability and scalability to meet the ever-changing demands of high-speed data acquisition and generation. Developers can further optimize SAR algorithm latency issues with the Fast Fourier Transform Co-Processor (FFTC) on the SoC. In summary, the enhanced performance, lower power consumption, and smaller footprint can reduce overall system cost by 50% and area by 66%.

How to eliminate SWaP limitations?

Synthetic aperture radar (SAR) has become the sensor of choice for aircraft or spacecraft imaging due to its high sensitivity, high accuracy, independence from weather and atmospheric conditions, and ground-penetrating capability.SAR systems require a large amount of digital processing power due to the intensive nature of signal processing. The limitations of SWaP under objective conditions place high efficiency requirements on the implementation of digital signal processing (DSP) algorithms. Adaptability is also critical in the implementation as SAR design and data usage requirements continue to evolve.

Higher implementation efficiency and adaptability requirements make system-on-chip (SoC), which combines programmable DSP cores with dedicated gas pedals, the processing platform of choice. SoC solutions provide strong signal processing capabilities at very low power levels to support avionics and defense (including radar), test and measurement, medical and other industrial applications. Based on TI's new KeyStone II multi-core architecture, the 66AK2L06 SoC integrates multiple processing elements, including TI's fixed and floating-point TMS320C66x digital signal processor cores, the fastest ARMCortexA15 core and advanced gas pedals. The 66AK2L06 SoC is equipped with a high-speed JESD204B direct interface to TI's high-speed analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and analog front ends (AFEs). The integrated software-programmable DFE for digital conversion and digital filtering further reduces power and space, producing optimal power per watt in a small footprint.

Get floating point accuracy without sacrificing performance?

The use of multiple DSP cores is a key technology that helps bring increasingly complex signal processing algorithms toward the forefront of waveform-intensive applications such as avionics, radar, sonar, test and measurement, and beamforming. Multi-core capabilities, coupled with the extended AccelerationPacs array and development tools for multi-core DSPs, enable high performance in a compact form factor at very low power. Avionics and defense applications require multicore DSPs to meet the evolving requirements of these mission-critical applications, including higher processing throughput, better resolution, improved accuracy, and integration of advanced interfaces. These needs rely on floating-point computing to achieve the required accuracy. Key to the KeyStone II architecture are its multi-core navigator, TeraNet and multi-core shared memory controller, thus providing a highly flexible and scalable solution for JESD add-on applications.

66AK2L06 key features.

-Two ARM Cortex-A15 RISC核@1.2GHz, 8400 DMIPS; ARM cores provide high performance RISC processing at ultra-low power levels to handle control and management functions

-四个TMS320C66x数字信号处理器核@1.2GHz with fixed-point and floating-point processing, providing 76 GFLOPs and 153 GMACS

-Integrated DFE technology (programmable filters, IQ imbalance correction, upsampling/downsampling, etc.) to ease the signal processing burden

-Advanced integrated network co-processor moves IP routing and IP termination away from the ARM/DSP core, enabling larger systems and efficient support for encryption and security

-FFTC increases the latency of FFT/iFFT execution to 8K points, providing better performance compared to fixed-point DSP implementations

-Integrated multicore shared memory controller (MSMC) with 2 megabytes of memory shared between cores and gas pedals

-Multicore Navigator provides single-core simplicity for multicore SoC software designs

-Ethernet switch with 4 x 1GbE ports

-Two single-lane PCIe Gen2 interfaces supporting up to 5 GBaud

-Highly integrated SoC reduces bill of materials (BOM) cost, system size and power consumption

-High-speed JESD204B-to-chip interface optimizes board layout (fewer channels and pins) and reduces power consumption for up to four channels (up to 7.37 Gbps SerDes speed) of multiple ADC/DAC/AFE interfaces.

JESD204B

In addition to greater integration at the silicon level, the 66AK2L06 SoC achieves a smaller BOM, reducing board production costs. Board design and layout is simplified by using the JESD204B serial communication link interface, which provides a high-throughput, low-pin-count serial link between on-board logic devices such as data converters (ADCs/DACs), field-programmable gate arrays (FPGAs), DSPs, SoCs, and application-specific integrated circuits (ASICs).

By embedding clocks in the data stream and including certain embedded algorithms to optimize the sampling of data bits, the JESD204B simplifies the path between devices and requires significantly fewer channels on the board. In contrast, to achieve the same throughput as JESD204B, a more prominent SerDes interface (e.g. PCI Express) would require more lines. Fewer lines means fewer I/O lanes on the device as well, resulting in a lower pin count and allowing for smaller package sizes.